Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance
We recently helped Thales evaluate the use of transaction level modeling for FPGA designs that use high-speed bus interfaces. We also helped our customer apply high-level test scenarios, verify 100% FPGA-level requirements by test and shorten their overall verification times. In this case study, you’ll hear from Thales on the verification challenges they were facing and how, with support from us, some great solutions we’re developed; all during a proof-of-concept project that has the potential to change the way all PCIe-based FPGA safety-critical designs are verified.
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