Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated Riviera-PRO™ to include the 2020.08 revision of the open-source VHDL verification methodology (OSVVM). This gives users of Aldec’s popular simulation platform access to OSVVM’s new requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions.
The latest version of Riviera-PRO (release 2020.10) also includes SystemVerilog and VHDL-2019 simulation enhancements. For SystemVerilog, the enhancements include extended support for 4-state integral packed unions, 2-state integral packed vectors, structures and unions, and fixed-size unpacked vectors, structures and unions. For VHDL-2019, the enhancements include support for arrays and records of protected types.
“In terms of VHDL-2019 support, Aldec is well ahead of the game,” comments Jim Lewis Director of VHDL Training at SynthWorks and IEEE 1076 VHDL Working Group Chair. “The company’s Riviera-PRO introduced several VHDL-2019 support features back in June 2020, and the enhancements announced today will facilitate the development of advanced verification capabilities.”
Sunil Sahoo, Aldec’s SW Product Manager, adds: “Aldec is committed to keeping Riviera-PRO a powerful simulation platform in its own right, and all enhancements introduced in any given release are in direct response to requests and suggestions from engineers. We’re also committed to the VHDL community and believe we currently provide more VHDL-2019 support than any other vendor.”
Debugging and performance enhancements are present in Riviera-PRO release 2020.10 too. These include support for new coverage pragmas within the Verilog compiler, randomization performance enhancements (for specific cases of random constraints) and an increase to the speed at which models are drawn into Riviera-PRO’s UVM Graph window.
Riviera-PRO 2020.10 is now available for download and evaluation.
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