Case Study: Aldec helps Thales evaluate TLM

Case Study: Aldec helps Thales evaluate TLM

Case Study: Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance We recently helped Thales evaluate the use of transaction level modeling for FPGA designs that use high-speed bus interfaces. We also...
Protecting IIoT devices from cyber attacks

Protecting IIoT devices from cyber attacks

Contributing to an ever-expanding attack surface and operating in an industry that is only just starting to see appropriate regulations, IIoT devices are vulnerable to cyberattacks. Michael Barrett, managing director of Nexus Industrial Memory, explains how devices...
Connected ….. and at Risk

Connected ….. and at Risk

View this article as a pdf IoT-enabled devices used in industrial applications are vulnerable to many forms of cyberattack. Michael Barrett, managing director of Nexus Industrial Memory, outlines some ways in which devices might be attacked and suggests how they can...
Aldec Adds UVM Generator to Riviera-PRO™

Aldec Adds UVM Generator to Riviera-PRO™

Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Henderson, NV – November 16, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC...