by Team Declaration | Nov 16, 2021 | Press Release
Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Henderson, NV – November 16, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC...
by Team Declaration | Oct 6, 2021 | Press Release
Andover, United Kingdom – Inseto, a leading technical distributor of equipment and materials, has invested in a Kulicke & Soffa (K&S) Asterion wedge bonder. Located in Inseto’s Process Development Laboratory along with materials test and plasma cleaning...
by Team Declaration | Sep 7, 2021 | Press Release
Interface with the Analog World… at Speed Logic-X launches industry’s first 4-in-4-out, 16-bit high-speed ADC/DAC FMC with LVDS digital interfaces Alphen a/d Rijn, Netherlands – September 7, 2021. Logic-X, a developer and supplier of adaptable compute acceleration...
by Team Declaration | Jul 19, 2021 | Press Release
Henderson, NV, USA – July 19, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched the HES-VU19PD-ZU7EV, an ASIC/SoC physical prototyping and hardware emulation board that can...
by Team Declaration | Jul 7, 2021 | Press Release
TySOM-M-MPFS250 is Aldec’s First Embedded Prototyping Platform Family Member to Feature a PolarFire® SoC FPGA Henderson, NV – July 7, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has...
by Team Declaration | Jun 2, 2021 | Press Release
Aldec Launches HES-DVM Proto ‘Cloud Edition’ – Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Henderson, NV, USA – June 2, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and...
