by Team Declaration | Mar 4, 2021 | Press Release
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added more than 60 new HDL rules to ALINT-PRO™’s DO-254 rules plug-in and has made several enhancements to the tool’s Design Entry capabilities to...
by Team Declaration | Mar 1, 2021 | Press Release
Inseto, a leading technical distributor of equipment and materials, has supplied Custom Interconnect Limited (CIL) with a Kulicke & Soffa Asterion large diameter wire / ribbon wedge bonder for use in the production of wide bandgap (WBG) semiconductor-based power...
by Team Declaration | Jan 20, 2021 | Press Release
Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for...
by Team Declaration | Dec 8, 2020 | Press Release
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated Riviera-PRO™ to include the 2020.08 revision of the open-source VHDL verification methodology (OSVVM). This gives users of Aldec’s popular...
by Team Declaration | Nov 24, 2020 | Press Release
Inseto, a leading technical distributor of equipment and materials, has supplied Compound Semiconductor Applications (CSA) Catapult with a Nordson DAGE Prospector micro-mechanical test station. Located in CSA’s Advanced Packaging laboratory, the tester is being used...
by Team Declaration | Oct 26, 2020 | Press Release
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added PYNQ Python Productivity for Zynq from Xilinx, Inc. to its TySOM family of Xilinx Zynq SoC based boards and its TySOM Embedded Development...